User guide

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Compiling and Elaborating Your Design
Library Mapping Files and Configurations
Library mapping and configurations are an LCA (Limited customer
Availability) feature and requires a special license. For more
information contact your Synopsys Applications Consultant.
Library mapping files are an alternative to the defacto standard way
of specifying Verilog library directories and files with the -v, -y, and
+libext+ext compile-time options and the ‘uselib compiler
directive.
Configurations use the contents of library mapping files to specify
what source code to use to resolve instances in other parts of your
source code.
Library mapping and configurations are described in Std 1364-2001
IEEE Verilog Hardware Description Language. There is additional
information on SystemVerilog in Std 1800-2005 IEEE Standard for
SystemVerilog - Unified Hardware Design, Specification,and
Verification Language.
It specifies that SystemVerilog interfaces can be assigned to a logical
libraries.
Library Mapping Files
A library mapping file enables you to specify logical libraries and
assign source files to these libraries. You can specify one or more
logical libraries in the library mapping file. If you specify more than
one logical library, you are also specifying the search order VCS uses
to resolve instances in your design.