User guide

IN-23
vcdpost utility 7-2
syntax 7-4
VCS
predefined text macro D-4
using Native Testbench 9-13
-vcs 21-10
vcs command line 1-13
+vcs+boundscheck 3-20, B-59
+vcs+dumpoff+t+ht C-18
+vcs+dumpon+t+ht C-18
+vcs+finish 4-8, C-13
+vcs+flush+all C-21
+vcs+flush+dump C-21
+vcs+flush+fopen C-21
+vcs+flush+log C-21
+vcs+grwavesoff C-18
+vcs+ignorestop 4-12, C-23
+vcs+initmem B-16
+vcs+initreg B-16
+vcs+learn+pli 1-20, 17-25–17-29, C-22
+vcs+lic+vcsi C-21
+vcs+lic+wait B-49, C-21
+vcs+mipd+noalias C-23
+vcs+mipdexpand B-36
+vcs+nostdout C-15
+vcs+saif_libcell 15-2
+vcs+stop 4-8, C-13
VCS/SystemC cosimulation interface
compiling for using 19-14, 19-20
supported port data types 19-8
VCS_CC A-3
VCS_CC environment variable 18-85
VCS_COM A-3
VCS_CPP environment variable 18-85
VCS_LD environment variable 18-85
VCS_LIC_EXPIRE_WARNING A-4
VCS_LOG A-4
‘vcs_mipdexpand D-7
‘vcs_mipdnoexpand D-7
VCS_NO_RT_STACK_TRACE A-4
VCS_RUNTIME A-4
VCS_SWIFT_NOTES A-4
+vcsi+lic+vcs C-21
+vcsi+lic+wait B-49
vcs.key file 9-13
vcsplit utility 7-26
vec32
storing four state Verilog data 18-15
vec32*
direct access for C/C++ functions
formal parameter type 18-20
-vera 1-17, B-23
Vera runtime options
vera_solver_mode 21-61
-vera_dbind B-23
vera_defines.vrh 21-7
+vera_load C-10
+vera_mload C-10
vera_portname 21-35
vera_portname argument to -ntb_opts B-13
verify 20-41, 20-42
Verilog
System Tasks
$vcdplustraceoff 6-21
$vcdplustraceon 6-21
Verilog module, compiling 21-27
Verilog parameter expansion 20-64
Verilog parameters in OVA 20-63
+verilog1995ext B-15
+verilog2001ext B-15
violation windows
using multiple non-overlapping 14-23–14-27
Virtual Interface Modports 24-208, 24-209
Virtual Interfaces 24-202
+vissymbols B-37
vlogan utility 19-17–19-19
VMC 1-22
void
C/C++ function return type 18-9
void functions 22-44
void()
example 24-88
semantics 24-89