User guide

IN-20
simv executable file 1-13
size PLI specification 17-9
$skew D-36
slicing arrays 22-16
SmartQ
reverse() 24-165, 24-166
solve-before
hard 24-92
Source Pane
Toolbar icon 5-5, 5-6
sparse memory models 2-25
specify blocks
disabling for an instance 13-39
suppressing 1-15, B-42
in specific module instances 13-40
specifying libraries on the link line B-51
$sreadmemb D-31
$sreadmemh D-31
stack, CLI command 9-9
starting DVE 5-7
static 24-45
step, CLI command 9-3
$stimen D-37
$stop D-32
stream generation
production definitions 24-118
stream generator
randseq 24-118
string
C/C++ function argument type 18-10
C/C++ function return type 18-9
input argument type 18-21
output and inout argument type 18-22
$strobe D-29
struct construct 22-10
structural drivers 22-20
structures 22-10
suspend_thread 21-4
-sv_pragma 23-42, B-11
-sverilog 22-69, B-9
SWIFT SmartModels
generating a template B-45
$sync$nor$plane D-36
-sysc 19-14, B-58
syscan utility 19-8–19-10
-syslib libs B-51
$system D-27
system tasks D-10–D-42
IEEE standard system tasks not
implemented D-42
System tasks and functions, OVA 20-68
SystemC
cosimulating with Verilog 19-1
$systemf D-27
SystemVerilog assertions 23-1–23-35
SystemVerilog functions 22-41
SystemVerilog tasks 22-40
+systemverilogext B-15
T
-t 21-10
task invocation from CLI 20-76
tasks in SystemVerilog 22-40
tb_timescale 21-34
tb_timescale argument to -ntb_opts B-13
tbreak CLI command 9-8
tchk ACC capability 17-14
temporal assertion files 20-4
temporal assertions 20-4
terminate, CLI command 9-10
test facilities 20-2
$test$plusargs D-39
testbench, compiling 21-27
testbench, loading 21-28
testing event coverage 20-6
this 24-64
thread, CLI command 9-7, 9-10
Threads 9-10
throughout operator 23-12
$time D-37
time
simulation