User guide

IN-10
triggering 3-4
verbose messages B-46
compiling, design, design, testbench and
Verilog module 21-27
compiling, design, shell, and Verilog module
21-27
concurrent assertions 23-1
consecutive repetition 23-6
context-dependent pragmas 20-60
continue
syntax 24-127
control constructs 21-4
control tasks, OVA debug 20-77
$countdrivers D-40
cover OVA directive 20-3
cover statements 23-25–23-28
coverag_group
embedded
syntax for defining 21-47
syntax for defining 21-47
Coverage 20-42
coverage
closed-loop analysis 21-46
coverage_load() 21-58, 24-243
single coverage_group 21-58, 24-243
cumulative 24-226
get_coverage() 21-51
get_inst_coverage() 21-51
instance-based 24-227
loading coverage data
coverage_instance() 21-59, 24-244
loading embedded coverage data
coverage_instance() 21-59, 24-244
open-loop analysis 21-46
coverage expressions 20-3
coverage, testing 20-6
coverage_group 21-46
predefined functions 24-230
inst_query() 24-230, 24-232, 24-233
coverage_group_attributes
at_least 21-49
coverage_instance() 21-59, 24-244
coverage_load 21-58, 24-243
-cpp B-52
+csdf+precomp+dir 13-8, B-35
+csdf+precomp+ext 13-8, B-35
+csdf+precompile 13-7, B-35
D
daidir directory 3-7
.daidir extension 3-7
data PLI specification 17-9
Data Type Mapping File
VCS/SystemC cosimulation interface 19-27
-debug B-30
Debug Control Tasks,OVA 20-77
-debug_all B-30
debugging
capability 9-13
debugging with CLI 9-13
debugging, OVA 20-37
declaring C/C++ functions in your Verilog code
18-6–18-12
default alias file 8-9
‘default_nettype D-3
‘define D-3
+define+macro=value 1-15, B-61
delay values
back annotating to your design D-39
+delay_mode_distributed 12-21, B-33
‘delay_mode_distributed D-6
+delay_mode_path 12-21, B-32
‘delay_mode_path D-5
+delay_mode_unit 12-22, B-32
‘delay_mode_unit D-6
+delay_mode_zero 12-22, B-32
‘delay_mode_zero D-6
delete, CLI command 9-8
+deleteprotected 25-11, B-54
Delta Cycle Information
Capturing delta cycle information 6-22
dep_check 21-33, 21-36
dep_check argument to -ntb_opts B-12