User guide

IN-8
$assert_monitor 23-64, D-25
$assert_monitor_off 23-64, D-26
$assert_monitor_on 23-64, D-26
assertion classes 21-63
Assertion failure, displaying message 20-75
assertion files 20-4
assertion pragmas 20-60
assertions 20-4
assertions, monitoring 20-70
$assertkill D-11
$assertoff D-11
$asserton D-11
$async$and$array D-36
+auto2protect 25-6, B-54
+auto3protect 25-6, B-54
+autoprotect 25-6, B-54
B
-B B-62
behavioral drivers 22-20
benefits of OpenVera Assertions 20-2
bit
C/C++ function argument type 18-10
C/C++ function return type 18-9
input argument type 18-21
output and inout argument type 18-22
reg data type in two-state simulation 18-6
bit data type 22-2
$bitstoreal D-28
break 9-5
usage in VSG 24-126
break and continue
break 24-126
break, CLI command 9-7
building OVA post-processor 20-26
byte data type 22-2
C
-C B-50, B-53
-c 21-10, B-51
C code generating
halt before compiling the generated C code
B-53
passing options to the compiler B-51
specifying B-51
specifying another compiler B-51
suppressing optimization for faster
compilation B-53
C compiler, environment variable specifying
the A-3
"C" specifier of direct access 18-7
C/C++ functions
argument direction 18-8, 18-9
argument type 18-8, 18-10
calling 18-12–18-14
declaring 18-6–18-12
extern declaration 18-7
in a Verilog environment 18-5–18-6
return range 18-8
return type 18-7, 18-9
using abstract access 18-29–18-77
access routines for 18-31–18-77
using direct access 18-20–18-29
examples 18-22–18-27
call PLI specification 17-9
calling C/C++ functions in your Verilog code
18-12–18-14
call-stack traversal 9-9
case
usage in VSG 24-125
case statements 24-125
cbk ACC capability 17-13, 17-19
cbka ACC capability 17-14
-CC B-51
-cc B-51
%CELL
use of 13-13
‘celldefine D-2
-CFLAGS B-51
char data type 22-2
char*
direct access for C/C++ functions
formal parameter type 18-20