User guide

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Compiling and Elaborating Your Design
The only SystemVerilog constructs that work with Radiant
Technology are SystemVerilog assertions that refer to signals with
Verilog-2001 data types, not the new data types in SystemVerilog.
Potential Differences in Coverage Metrics
VCS supports coverage metrics with Radiant Technology and you
can enter both the +rad and -cm compile-time options. However,
Synopsys does not recommend comparing coverage between two
simulation runs when only one simulation was compiled for Radiant
Technology.
The Radiant Technology optimizations, though not changing the
simulation results, can change the coverage results.
Compilation Performance With Radiant Technology
Using Radiant Technology incurs longer incremental compile times
because the analysis performed by Radiant Technology occurs every
time you recompile the design even when only a few modules have
changed. However, VCS only performs the code generation phase
on the parts of the design that have actually changed. Therefore the
incremental compile times are longer when you use Radiant
Technology but shorter than a full recompilation of the design.
Applying Radiant Technology to Parts of the Design
The configuration file enables you to apply Radiant optimizations
selectively to different parts of your design. You can enable or disable
Radiant optimizations for all instances of a module, specific instances
of a module, or specific signals.