User guide

D-42
Compiler Directives and System Tasks
$xzcheckoff
Suppress the warning message every time VCS evaluates a
conditional expression to have an X or Z value.
Syntax:
$xzcheckoff(hierarchical_name,level_number)
hierarchical_name
Hierarchical name of the module instance, that is, the top-level
instance of the subhierarchy for which you want to enable
checking.
level_number
Number of levels down in the subhierarchy from the specified
module instance. Checking is also enabled for the instances on
these levels.
IEEE Standard System Tasks Not Yet Implemented in
VCS
The following Verilog system tasks are included in the IEEE Std 1364-
2001 standards but are not yet implemented in VCS:
$dist_chi_square $dist_erlang
$dist_t $nochange