User guide

D-25
Compiler Directives and System Tasks
level_number
Specifies the number of hierarchy scope levels for which to
record signal value changes (a zero value records all scope
instances to the end of the hierarchy; default is all).
module_instance
Specifies the name of the scope for which to record signal value
changes (default is all).
net_or_variable
Specifies the name of the signal for which to record signal value
changes (default is all).
$vcdplustraceoff
Stops recording, in the VPD file, the order of statement execution
in the specified module instance. Syntax:
$vcdplustraceoff(module_instance);
$vcdplustraceon
Starts recording, in the VPD file, the order of statement execution
in the specified module instance and the module instances
hierarchically under it. Syntax:
$vcdplustraceon[(module_instance)];
System Tasks for SystemVerilog Assertions
IMPORTANT:
Enter these system tasks in an initial block. Do not enter
them in an always block.
$assert_monitor
Analogous to the standard $monitor system task; it continually
monitors specified assertions and displays what is happening with
them (you can only have it display on the next clock of the
assertion). Its syntax is as follows: