User guide

D-12
Compiler Directives and System Tasks
System Tasks for SystemVerilog Assertions
$onehot
Returns true if only one bit in the expression is true. See the
Accellera SystemVerilog 3.1 LRM, page 228.
$onehot0
Returns true if at the most one bit of the expression is true (also
returns true if none of the bits are true). See the Accellera
SystemVerilog 3.1 LRM, page 228.
$isunknown
Returns true if one of the bits in the expression has an X value.
See the Accellera SystemVerilog 3.1 LRM, page 228.
System Tasks for VCD Files
VCD files are ASCII files that contain a record of a net or register’s
transition times and values. There are a number of third party products
that read VCD files to show you simulation results. VCS has the
following system tasks for specifying the names and contents of these
files:
$dumpall
Creates a checkpoint in the VCD file. When VCS executes this
system task, VCS writes the current values of all specified nets
and registers into the VCD file, whether there is a value change
at this time or not. See IEEE std 1364-2001 page 327.
$dumpoff
Stops recording value change information in the VCD file. See
IEEE std 1364-2001 page 326.