User guide

D-11
Compiler Directives and System Tasks
System Tasks for SystemVerilog Assertions Severity
$fatal
Generates a runtime fatal assertion error. See the Accellera
SystemVerilog 3.1 LRM, page 227.
$error
Generates a runtime assertion error. See the Accellera
SystemVerilog 3.1 LRM, page 227.
$warning
Generates a runtime warning message. See the Accellera
SystemVerilog 3.1 LRM, page 227.
$info
Generates an information message. See the Accellera
SystemVerilog 3.1 LRM, page 227.
System Tasks for SystemVerilog Assertions Control
$assertoff
Tells VCS to stop monitoring any of the specified assertions that
start at a subsequent simulation time. See the Accellera
SystemVerilog 3.1 LRM, page 228.
$assertkill
Tells VCS to stop monitoring any of the specified assertions that
start at a subsequent simulation time, and stop the execution of
any of these assertions that are now occurring. See the Accellera
SystemVerilog 3.1 LRM, page 228.
$asserton
Tells VCS to resume the monitoring of assertions that it stopped
monitoring due to a previous $assertoff or $assertkill
system task. See the Accellera SystemVerilog 3.1 LRM, page 228.