User guide

C-61
Compile-Time Options
Hardware Modeling
-lmc-hm
Compiles a design that instantiates a hardware model. Including
this option is an alternative to specifying the lmvc.tab PLI table
file and the lmvc.o lm_sfi.a object file and library that you need for
hardware modeling.
Changing Source File Identifiers to Upper Case
-u
Changes all the characters in identifiers to uppercase. It does not
change identifiers in quoted strings such as the first argument to
the $monitor system task. You do not see this change in the DVE
Source window but you do see it in all the other DVE windows.
Defining a Text Macro
+define+macro=value+
Defines a text macro in your source code to a value or character
string. You can test for this definition in your Verilog source code
using the ‘ifdef compiler directive. If there are blank spaces in
the character string then you must enclose it in quotation marks.
For example:
vcs design.v +define+USELIB="dir=dir1 dir=dir2"
The macro is used in a ‘uselib compiler directive:
‘uselib ‘USELIB libext+.v