User guide

C-59
Compile-Time Options
TetraMAX
+tetramax
Enables simulation of TetraMAX’s testbench in zero delay mode.
Make Accessing an Undeclared Bit an Error Condition
+vcs+boundscheck
Changes reading from or writing to an undeclared bit to an error
condition instead of a warning condition.
Treat Output Ports As Inout Ports
+spl_read
Tells VCS to treat output ports as “inout” in order to facilitate more
accurate multi-driver contention analysis across module
boundaries. This option can have an adverse impact on runtime
performance.
Allow Inout Port Connection Width Mismatches
+noerrorIOPCWM
Changes the error condition, when a signal is wider or narrower
than the inout port to which it is connected, to a warning condition,
thus allowing VCS to create the simv executable after displaying
the warning message.
Specifying a VCD File
+vcs+dumpvars
A substitute for entering the $dumpvars system task, without
arguments, in your Verilog code.