User guide

C-43
Compile-Time Options
display of warning messages when VCS finds a timing violation
that you specified in a timing check.
+no_tchk_msg
Disables display of timing violations but does not disable the
toggling of notifier registers in timing checks. This is also a runtime
option.
Options to Enable the VCS DirectC Interface
+vc+[abstract+allhdrs+list]
The +vc option enables extern declarations of C/C++ functions
and calling these functions in your source code. See The VCS
DirectC Interface User Guide. The optional suffixes to this option
are as follows:
+abstract
Enables abstract access through vc_handles.
+allhdrs
Writes the vc_hdrs.h file that contains external function
declarations that you can use in your Verilog code.
+list
Displays all the C/C++ functions that you called in your Verilog
source code.
Options for Negative Timing Checks
+neg_tchk
Enables negative values in timing checks. See “Enabling
Negative Timing Checks” on page 14-13.
+old_ntc
Prevents the other timing checks from using delayed versions of