User guide

C-37
Compile-Time Options
As an alternative to using this option, you can use the
‘vcs_mipdexpand compiler directive or you can enter the mipb
ACC capability in your PLI table file. For example:
$sdf_annotate call=sdf_annotate_call
acc+=rw,mipb:top_level_mod+
When you compile the SDF file (recommended) the
backannotation of the delay values for individual bits of a port does
not require this option.
Options for Profiling Your Design
+prof
Specifies that VCS writes the vcs.prof file during simulation. This
file tells you which module definitions, module instances, and
Verilog constructs in your design use the most CPU time. See
“Profiling the Simulation” on page 4-13.
+vissymbols
Makes symbols visible when you are using the prof or gprof
program (not the VCS profiler that is enabled by the +prof option)
to profile generated code.