User guide

C-30
Compile-Time Options
-cm_tgl mda
Enables toggle coverage for Verilog-2001 multidimensional
arrays (MDAs) and SystemVerilog unpacked MDAs. Not required
for SystemVerilog packed MDAs.
Options for Discovery Visual Environment and UCLI
-debug
Enables DVE and UCLI debugging. This option does not enable
line stepping.
-debug_all
Enables DVE and UCLI debugging including line stepping.
-ucli
Forces runtime to go into UCLI mode by default.
-gui
When used at compile time, starts DVE at runtime.
-debug_pp
Enables minimal debug access so as to allow VPD dumping and
assertion debug. You can view the results inside DVE in
postprocessing mode.
Creates a VPD file (when used with the Verilog system task
$vcdpluson) and enables DVE for postprocessing a design.
Using -debug_pp can save compilation time by eliminating the
overhead of compiling with -debug and -debug_all.
-PP
Enables you to enter system tasks like $vcdpluson in your
Verilog source code to create a VPD file during simulation. This
option minimizes net data details for faster post-processing.