User guide

3-20
Compiling and Elaborating Your Design
Making Accessing an Out of Range Bit an Error
Condition
By default it is a warning condition if your code assigns a value to, or
reads the value of, a bit of a signal, or an element in a memory or
multidimensional array, that was not in the declaration of the signal,
memory, or array.
For example:
reg [1:0] r1;
.
.
.
initial
r1[2] = 1;
In this case, there is no bit 2 in the declaration of reg r1. VCS displays
a warning message but continues to compile the code and link
together the simv executable. The following is an example of this
warning message:
Warning-[SIOB] Select index out of bounds
in module module_name
"source_file.v", line_number: signal[bit]
You can use the +vcs+boundscheck compile-time option to tell
VCS to make accessing a bit or element that is outside the declared
range to be an error condition, so that VCS does not create the new
simv executable.
The following is an example of the error message VCS displays when
you enter this option and access an undeclared bit:
Error-[SIOB] Select index out of bounds
in module module_name