User guide

C-13
Compile-Time Options
print_deps
Tells VCS to display the dependencies for the source files on
the screen or in the specified file. Enter this argument with the
dep_check argument.
tb_timescale=value
Specifies an overriding timescale for the testbench. The
timescale is in the Verilog format (for example, 10ns/10ns).
tokens
Preprocesses the OpenVera files to generate two files,
tokens.vr and tokens.vrp. The tokens.vr contains
the preprocessed result of the non-encrypted OpenVera files,
while the tokens.vrp contains the preprocessed result of the
encrypted OpenVera files. If there is no encrypted OpenVera
file, VCS sends all the OpenVera preprocessed result to the
tokens.vr file.
use_sigprop
Enables the signal property access functions. For example,
vera_get_ifc_name().
vera_portname
Specifies the following:
- The Vera shell module name is named vera_shell.
- The interface ports are named ifc_signal.
- Bind signals are named, for example, as: \if_signal[3:0].
For example, if “adder” is the name of the interface, specifying
-ntb_opts vera_portname causes VCS to use the
following shell module:
vera_shell vshell(
.SystemClock (SystemClock),
.adder_inp1 (inp1),
.adder_inp2 (inp2),