User guide

C-11
Compile-Time Options
dumpoff
Disables the dumping of SVA information in the VPD file during
simulation.
vpiSeqBeginTime
Enables you to see the simulation time that a SystemVerilog
assertion sequence starts when using Debussy.
vpiSeqFail
Enables you to see the simulation time that a SystemVerilog
assertion sequence doesn’t match when using Debussy.
-sv_pragma
Tells VCS to compile the SystemVerilog Assertions code that
follows the sv_pragma keyword in a single line or multi-line
comment.
Options for OpenVera Native Testbench
+debug_all
Enables you to use the OpenVera testbench GUI.
-ntb
Enables the use of the OpenVera testbench language constructs
described in the OpenVera Language Reference Manual: Native
Testbench.
-ntb_cmp
Compiles and generates the testbench shell (file.vshell) and
shared object files. Use this option when compiling the .vr file
separately from the design files.
-ntb_define macro
Specifies any OpenVera macro name on the command line. You
can specify multiple macro names using the plus (+) character.