User guide

C-6
Compile-Time Options
in a source file in a Verilog library directory that resolves a module
instantiation statement that VCS read in your source files, a library
file, or in another file in a library directory. The message is as
follows:
Resolving module "module_identifier"
By default, VCS does not display this message when it finds a
module definition in a Verilog library file that resolves a module
instantiation statement.
Options for Incremental Compilation
-Marchive=number_of_module_definitions
By default, VCS compiles module definitions into individual object
files and sends all the object files in a command line to the linker.
Some platforms use a fixed-length buffer for the command line
and if VCS sends too long a list of object files this buffer overflows
and the link fails. A solution to this problem is to have the linker
create temporary object files containing more than one module
definition so there are fewer object files on the linker command
line. You enable creating these temporary object files, and specify
how many module definitions are in these files, with this option.
Using this option briefly doubles the amount of disk space used
by the linker because the object files containing more than one
module definition are copies of the object files for each module
definition. After the linker creates the simv executable it deletes
the temporary object files.
-Mupdate[=0]
By default, VCS overwrites the makefile between compilations. If
you wish to preserve the makefile between compilations, enter
the 0 argument with this option. Entering this option without the 0