User guide

C-4
Compile-Time Options
• Options for Controlling Messages
• Options for Cell Definition
• Options for Licensing
• Options for Controlling the Assembler
• Options for Controlling the Linker
• Options for Controlling the C Compiler
• Options for Source Protection
• Options for Mixed Analog/Digital Simulation
• Options for Changing Parameter Values
• “Checking for X and Z Values in Conditional Expressions” on page
B-57
• Options to Specify the Time Scale
• General Options
Options for Accessing Verilog Libraries
-v filename
Specifies a Verilog library file. VCS looks in this file for definitions
of the module and UDP instances that VCS found in your source
code but for which it did not find the corresponding module or UDP
definitions in your source code.
-y directory
Specifies a Verilog library directory. VCS looks in the source files
in this directory for definitions of the module and UDP instances
that VCS found in your source code but for which it did not find
the corresponding module or UDP definitions in your source code.