User guide

B-1
Compile-Time Options
B
Compile-Time Options B
The vcs command performs compilation of your designs and creates
a simulation executable. Compiled event code is generated and used
by default. The generated simulation executable, called simv, can
then be used to run multiple simulations.
This section describes the vcs command and related options.
Syntax:
vcs source_files [source_or_object_files] options
Here:
source_files
The Verilog or OVA source files for your design separated by
spaces.