User guide

3-17
Compiling and Elaborating Your Design
Example 5 False Negative Example
module test;
reg r1;
initial
begin
r1=1'b0;
#1 r1<=1'b1;
r1=1'bx;
end
always @ (r1)
begin
if (r1)
$display("\n r1 true at %0t\n",$time);
else
$display("\n r1 false at %0t\n",$time);
end
endmodule
If you consider these warning messages to be false negatives, use
the nofalseneg argument to the -xzcheck option to suppress the
messages.
For example:
vcs example.v -xzcheck nofalseneg
If you compile and simulate example1 or example2 with the -
xzcheck compile-time option, but without the nofalseneg
argument, VCS displays the following warning about signal r1
transitioning to an X or Z value:
r1 false at 0
Warning: 'r1' within scope test in source.v: 13 goes to x/
z at time 1