User guide

3-16
Compiling and Elaborating Your Design
Filtering Out False Negatives
By default, if a signal in a conditional expression transitions to an X
or Z value and then to 0 or 1 in the same simulation time step, VCS
displays the warning.
Example 1
In this example, VCS displays the warning message when reg r1
transitions from 0 to X to 1 during simulation time 1.
Example 4 False Negative Example
module test;
reg r1;
initial
begin
r1=1'b0;
#1 r1=1'bx;
#0 r1=1'b1;
end
always @ (r1)
begin
if (r1)
$display("\n r1 true at %0t\n",$time);
else
$display("\n r1 false at %0t\n",$time);
end
endmodule
Example 2
In this example, VCS displays the warning message when reg r1
transitions from 1 to X during simulation time 1.