User guide

25-14
Source Protection
if (acc_object_of_type(obj, accProtected)) {
printf("object %s is from a protected module\n",
acc_fetch_name(obj));
}
If the object passed to acc_object_of_type() is a design object in
a module, a port or register for example, the status of the parent
module will be returned.
Mangling Source Files
The purpose of mangling is to create a Verilog source file that is
functionally the same as an original Verilog file or set of Verilog files,
but in the new Verilog source file the identifiers (module, instance, or
signal names) no longer make any sense and all the comments are
removed, making it very difficult to understand the design contained
in the new file.
Mangling does not change the structure of the source description, in
the new mangled file the keywords and syntax remain the same as
those in the original Verilog file or set of Verilog files.
One use for this new Verilog source file is that you can send the
mangled file to [e-mail] so that our Corporate
Applications Engineers can examine problems you are experiencing
while maintaining the only intelligible copy of your design at your site.
The name of the mangled source file you create is tokens.v.
You mangle your source description with the -Xmangle or
-Xmangle=number option. When you enter this option, VCS creates
a file named tokens.v
that contains the mangled source description.