User guide

25-7
Source Protection
• VCS inserts the ‘protected compiler directive after the module
header and the ‘endprotected compiler directive before the
endmodule keyword. VCS encrypts the Verilog source between
the
‘protected and ‘endprotected compiler directives that it
inserts.
The following is an example of a Verilog source file whose entire
contents you want to encrypt with source protection:
module top( inp, outp);
parameter size=8;
input [size-1:0] inp;
output [size-1:0] outp;
reg [7:0] count;
assign outp = count;
parameter stoptime=100;
always
begin:counter
reg [size-1:0] int;
count = 0;
int = inp;
while (int)
begin
if (int [0]) count = count + 1;
int = int >> 1;
end
#stoptime $stop;
end
endmodule
The following is an example of the contents of the new source file
VCS creates when you run source protection with the
+auto2protect
option:
module top( inp, outp);
`protected
\,MGH?JR[D?0R_D#+XJ(MQD#HgXV@ZUVI2+HT)1OS)C8#L7OA[9ge#^#5@WO0P_<
,Y)[^ZVDDCBf<EB?2(=)>S#aSR58?]Qgg6\#OOf<^&#5.+RK[6<#2&X>SZM:)F9>
VLf:FHRSd[QP=WCC\gA;=g5M=>PG5EDUaZ:#/If[CTXV9RKJNNOf]>Cfgg[4&W.f
=2FD]<,R0?@:B0R:?\4fP_dgaGgF_IB9MV#E1M?b2)Cd._<:&@,KV\a5:Q3D]CPL
[9HDe2.gQYL0;\_Y^V\a;_Ag-fP;+K\;GUU/:HXFf;gaGJ1fO8_f1M)eGF8LRRY]