User guide

25-5
Source Protection
always
begin:counter
`protect //begin protected region
reg [7:0] int;
count = 0;
int = inp;
while (int)
begin
if (int [0]) count = count + 1;
int = int >> 1;
end
`endprotect //end protected region
end
endmodule
The following is the contents of the new file after you run source
protection with the +protect option:
module top( inp, outp);
input [7:0] inp;
output [7:0] outp;
reg [7:0] count;
assign outp = count;
always
begin:counter
`protected
%%AqDtf%,%,%,%,%,%,-%,%,UB@%,|%5%B%<z%,NIS%A-%,%,DH
?%,NIW%A-%,%,PONKB%,%4NIS%3-%,%,%,%,EB@NI-%,%,%,%,%
RIS%,%?%,DHRIS%,%1%,%;%A-%,%,%,%,%,%,NIS%,%?%,NIS%
,%,$
`endprotected
//end protected region
end
endmodule
Encrypting The Entire Source Description
You can encrypt all the modules and UDPs in the new Verilog source
files that VCS creates without yourself entering
‘protect and
‘endprotect
compiler directives in your source code.