User guide

25-4
Source Protection
Encrypting Specified Regions
You can control what part of your source VCS encrypts in the new
files and which part remains readable. To do so you do the following:
1. Enclose the part of your source that you want VCS to encrypt
between the ‘protect and the ‘endprotect compiler directives.
2. Include the +protect option on the vcs command line.
When you run VCS with the +protect option:
- VCS creates new files for the Verilog source files you specify
on the vcs command line.
- VCS replaces the ‘protect
and ‘endprotect compiler
directives with the ‘protected and ‘endprotected compiler
directives and encrypts all the Verilog source description
between these ‘protected and ‘endprotected
compiler
directives.
The new files have the same filename except that VCS appends a
“p” to the filename extension of the new files. For example, if you run
source protection for a source file named my_design.v, VCS names
the new file with encrypted source my_design.vp. This is the default
filename extension for the new file. You can specify a different
extension.
The following is an example of a Verilog source file with a region of
the source that you want protected:
module top( inp, outp);
input [7:0] inp;
output [7:0] outp;
reg [7:0] count;
assign outp = count;