User guide

25-2
Source Protection
• Creating a VMC model from source description:
A VMC model is an executable binary that you compile from your
Verilog model. To simulate the VMC model you link it to VCS. VMC
is a separate Synopsys product.
These source protection methods vary in the levels of security they
provide, their impact on performance, platform and vendor
independence, and PLI and CLI access as described in Table 25-1,
Source Protection Methods.
Note:
This chapter describes mangling and encrypting. For information
on creating a VMC model see the VMC User’s Guide.
Table 25-1 Source Protection Methods
Method Level of Security Performance Platform
Independence
Vendor
Independence
PLI and CLI
Access
Mangling Alters only the
identifiers. You
can read the
structure of the
source
description.
Same as
VCS or third
party Verilog
simulator
Yes, the output
is an ASCII file
Yes, you can
simulate the
resulting model
in any Verilog
simulator
Yes, however
the identifiers
are difficult to
understand.
Encrypting Alters the entire
source
description but
some identifiers
can be seen in
generated C code
Same as
VCS
Yes, the output
is an ASCII file
No, the
encrypted
output is in a
format that only
VCS can read.
Yes, but only if
you know the
identifiers
before they
were encrypted
VMC Absolute, the
output is an
executable binary
Some impact
on small and
active VMC
models
No, you can
only simulate a
VMC model on
the platform
that was used
to generate it.
Yes, using
standard PLI
access
No access into
VMC models