User guide

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SystemVerilog Testbench Constructs
SystemVerilog File
This SV code calls C_test(), which then calls the blocking APB_Write
task in SystemVerilog. The APB_Write task has a simple semaphore
to ensure unique access.
import "DPI" context task c_test(input int base_addr);
program top;
semaphore bus_sem = new(1);
export "DPI" task apb_write;
task apb_write(input int addr, data);
bus_sem.get(1);
#10 $display("VLOG : APB Write : Addr = %x, Data = %x
", addr, data);
#10 ifc.addr <= addr;
#10 ifc.data <= data;
bus_sem.put(1);
endtask
initial begin
fork
c_test(32'h1000);
c_test(32'h2000);
join
end
endprogram
The VCS command line compiles the files.
vcs -sverilog top.sv c_test.c -R