User guide

24-252
SystemVerilog Testbench Constructs
Example:
import "DPI" context task c_task(input int addr);
program top;
initial c_task(1000);
initial c_task(2000);
endprogram
#include <svdpi.h>
void c_task(int addr) {
...
}
vcs -sverilog top.sv c_task.c
Export Functions- C/C++ Calling SystemVerilog
The export tasks/functions are SystemVerilog tasks/functions that
can be called from C/C++ languages. You must declare them before
you can use them. Export function declarations are allowed only in
the scope in which the function is defined and only one declaration
per function is allowed in a given scope.
The export functions and tasks have the same restrictions on
argument types and return values as the import functions.
Syntax:
Declaration :
export "DPI" [cname =] function name (args);
export "DPI" [cname =] task name (args);