User guide

24-239
SystemVerilog Testbench Constructs
Total 3 3 100.00
cp1 3 3 100.00 100 1
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Summary for variable cp1
Expected Covered Percent
User Defined Bins 3 3 100.00
User Defined Bins for cp1
Bins name count at least
auto_yellow 2 1
auto_blue 2 1
auto_red 4 1
The report begins with a summary of the coverage for the
covershapes created. There is 100% coverage, meaning that VCS
saw all possible values for the coverage point(s) in the covergroup.
For coverage point cp1, the report says the following:
• The coverage point, in this case variable my_color, reached all
its possible values.
• There were no user defined bins.
• VCS created bins for the coverage point named auto_blue,
auto_red, and auto_yellow, all named after the members of the
enumerated type colors, blue, red, and yellow.
• There were four hits for bin auto_red, this means that during
simulation, there were four clocking events (rising edge on signal
clk) where VCS detected that the value of the variable my_color
was red.
• There were two hits for bins auto_blue and auto_yellow.