User guide

24-234
SystemVerilog Testbench Constructs
initial
begin
cov1 = new(2);
$display("Original instance name is %s\n",
cov1.option.name);
cov1.set_inst_name("new_cov1");//change instance name
$display("Instance name after calling set_inst_name()
is %s\n", cov1.option.name);
end
endprogram
Output of the program is:
Original instance name is cov1
Instance name after calling set_inst_name() is new_cov1
sample()
sample() triggers sampling of the covergroup instance. Return
void.
program test();
reg clk = 0;
reg [2:0] var = 3'b001;
covergroup covType ();
cp1: coverpoint var {
bins s0 = { 0 };
bins s1 = { 1 };
bins s2 = { 2 };
bins s3 = { 3 };
bins s4 = { 4 };
bins s5 = { 5 };
bins s6 = { 6 };
bins s7 = { 7 };
}
endgroup