User guide

24-223
SystemVerilog Testbench Constructs
}
VCS displays an error message when the coverage point reaches
these values or makes these transitions.
Defining Cross Coverage
Cross coverage is when there are two coverage points that you want
VCS to compare to see if all the possible combinations of the possible
values of the two coverage points occurred during simulation.
Consider the following example:
program prog;
bit clk;
bit [1:0] bit1,bit2;
covergroup cg1 @(posedge clk);
bit1: coverpoint bit1;
bit2: coverpoint bit2;
bit1Xbit2: cross bit1, bit2;
endgroup
cg1 cg1_1 = new;
initial
begin
clk = 0;
repeat (200)
begin
bit1 = $random();
bit2 = $random();
#5 clk = ~clk;
#5 clk = ~clk;
end
end
endprogram