User guide

24-219
SystemVerilog Testbench Constructs
Example :
bit [1:0] cp_exp1;
// type evaluates to the value range of 0 to 3
bit signed [2:0] cp_exp2;
// type evaluates to the value range of -4 to 3
covergroup g1 @(posedge clk);
coverpoint cp_exp1 {
bins b_exp1 = {1, [2:5] };
bins b_exp2 = { -1, [1:4]};
}
coverpoint cp_exp2 {
bins b_exp3 = {1, [2:5], [6:10] };
}
endgroup
Warnings Issued and their resolutions
A warning is issued for the bin
b_exp1 since the range [2:5] exceeds
the upper bound for the coverpoint
cp_exp1. The bin b_exp1 is
evaluated and adjusted to the max value of the coverpoint. Here the
bin
b_exp1 is evaluated as {1, [2:3]}.
A warning is issued for the bin
b_exp2 since the singleton value -1
exceeds the upper bound for the coverpoint
cp_exp1. The bin b_exp2
is evaluated such that the -1 value is not considered. Here the bin
b_exp2 is evaluated as {[1:3]}.
A warning is issued for the bin
b_exp3 since the range [2:5] and
[6:10] exceeds the upper bound for the coverpoint
cp_exp3. The
bin
b_exp3 is evaluated such that the range [2:5] is adjusted to the
max value of the coverpoint and the range [6:10] is completely
ignored. Here the bin
b_exp3 is evaluated as {1, [2:3]}.