User guide

24-215
SystemVerilog Testbench Constructs
VCS collects all the coverage data during simulation and generates
a database. VCS provides a tool to read the database and generate
text or HTML reports.
The covergroup Construct
The covergroup construct specifies the set of cover points of
interest, crosses of these cover points and the clocking event that
tells VCS when to sample these cover points during simulation.
A covergroup can be declared inside a module or the program block.
When declared inside a module they generate a separate instance
of the covergroup for each instance of the module created.
program prog;
bit clk = 0;
enum {red, blue, yellow} colors;
colors my_color;
covergroup cg1 @(posedge clk);
cp1 : coverpoint my_color;
endgroup
cg1 cg1_1 = new;
initial
repeat (15)
#5 clk = ~clk;
initial
begin
#40 my_color = blue;
#23 my_color = yellow;
end