User guide

24-214
SystemVerilog Testbench Constructs
begin
virtual I vi;
vi.data <= 1;
end
• NULL assignment
virtual I vi = NULL;
Not Yet Implemented
• Named type that involves virtual interface
- typedef struct {reg rl; virtual I ii} T;
- typedef virtual I T;
• Comparison of vi variables
By definition, vi1 == vi2 iff they refer to the same instance of an
interface (or both NULL).
• VI variables defined in the design.
• Class member variable access through VI when is declared in
parent interface.
Coverage
The VCS implementation of SystemVerilog supports the
covergroup construct. Covergroups are specified by the user. They
allow the system to monitor values and transitions for variables and
signals. They also enable cross coverage between variables and
signals.