User guide

3-10
Compiling and Elaborating Your Design
Without the +noerrorIOPCWM compile-time option, VCS displays
the following error message and does not create the simv
executable:
Error-[IOPCWM] Inout Port connection width mismatch
The following 8-bit expression is connected to 16-bit
port "gk" of
module "dev", instance "dev1".
If you include the +noerrorIOPCWM compile-time option, VCS
displays the following warning message and creates the simv
executable:
Warning-[IOPCWM] Inout Port connection width mismatch.
Connecting inout ports to
mismatched width nets has unpredictable results and will
not be permitted in future releases.
The following 8-bit expression is connected to 16-bit
port "pote" ofmodule "dev", instance "dev1".
Expression: w1
"exp1.v", line_number
Using Lint
The +lint compile-time option displays lint messages. These
messages help you to write very clean Verilog code. The following is
an example of a lint message:
Lint-[GCWM] Gate connection width mismatch