User guide

24-213
SystemVerilog Testbench Constructs
endinterface
....
program P;
virtual SyncBus vi;
...
initial vi.cb.w <= 1;
...
endprogram
In this case the assignment executes in accordance with the clocking
block semantics.
Event Expression/Structure
Consider SyncBus as defined in the section “Clocking Block” .
task wait_on_expr(virtual SyncBus vi1, virtual SyncBus vi2);
@(posedge (vi1.a & vi2.a))
$display(vi1.b, vi2.b);
endtask
There is a principal difference between Vera and SV in that the “@”
operator can have an operand that is a complex expression. We
support all event expression that involve virtual interface variables.
Structures inside an interface can also be referred to by means of a
virtual interface.
Null Comparison
We support:
• Comparison of vi variable with NULL.
• Runtime error if uninitialized virtual interface is used