User guide

24-212

SystemVerilog Testbench Constructs

program p;

virtual intf VI[3:0];

initial begin

VI = top.INTF; //aggregate assignment

$display(VI[0].k);

t1(VI);//passing whole VI array to task

end

task t1(virtual intf vif[3:0]);

$display(vif[0].k);

endtask

endprogram

module top;

intf INTF [3:0]();

endmodule

The output of this program is:

Driving/sampling of interface signals through Virtual Interface array

elements is possible.For example:

VI[0].k <= 10; //valid drive

@ (VI[0].k); //valid wait

Clocking Block

Similarly to modport, a clocking block inside interface instance can

be referred to by a virtual variable:

interface SyncBus(input bit clk);

wire w;

clocking cb @(posedge clk);

output w;

endclocking