User guide

24-210
SystemVerilog Testbench Constructs
interface intf(input clk);
int d;
clocking cb @(posedge clk);
default input #2 output #2;
inout d;
endclocking
modport CB(clocking cb); //synchronous testbench modport
modport master(inout d); //asynchronous testbench modport
endinterface
module top;
bit clk;
always #5 clk = ~clk;
intf INTF(clk);
tb TB(INTF);
endmodule
program tb(intf.CB ckb); //CB type modport is used to pass
//clocking information with interface signals
virtual intf.CB x = ckb;
initial
#200 $finish;
initial begin
x.cb.d <= 1; @(x.cb.d); $display($time,,x.cb.d);
x.cb.d <= 2; @(x.cb.d); $display($time,,x.cb.d);
//x.d <= 3; illegal as signal not visible via
//CB modport
end
endprogram
The output of this example is:
15 1
25 2