User guide

24-209
SystemVerilog Testbench Constructs
writing assignments are subject to modport direction enforcement so
that, for example, “sb.req = 1" would become illegal now (violates
input direction of the modport REQ).
Driving a Net Using a Virtual Interface
There are two ways of driving interface nets from a testbench. These
are:
• Via clocking block:
interface intf(input bit clk);
wire w1;
clocking cb @ (posedge clk);
output w1;
endclocking
endinterface
• By including a driver updated by a continuous assignment from a
variable within the interface
interface intf;
wire w1;
reg r1;
assign w1 = r1;
endinterface
This example demonstrates driving an interface net in a design.
Virtual Interface Modports and Clocking Blocks
You can reference an interface clocking block signal directly by using
dot notation. The clocking information can be sent to the testbench
only through modport if interface is having modports. The following
example demonstrates this.