User guide

24-206
SystemVerilog Testbench Constructs
else
begin
bit1=0;
$display("failure at %0t in %m\n",$time);
end
e2: expect (@(posedge clk) ##[1:9] in1 && in2)
begin
bit1=1;
$display("success at %0t in %m\n",$time);
end
else
begin
bit1=0;
$display("failure at %0t in %m\n",$time);
end
e3: expect (@(posedge clk) ##1 in1 && in2 [*5])
begin
bit1=1;
$display("success at %0t in %m\n",$time);
end
else
begin
bit1=0;
$display("failure at %0t in %m\n",$time);
end
end
endprogram
The program block includes an elementary clocking block, specifying
a clocking event on the rising edge of clk, and no skew for signals in1
and in2.
The $display system tasks in the failure and success action blocks
display the following:
failure at 15 in test.tbpb1.e1
success at 65 in test.tbpb1.e2