User guide

24-205
SystemVerilog Testbench Constructs
[*] is the consecutive repeat operator. This expect statement calls
for waiting a clock delay and then seeing if the expression is true, and
doing both of these things five times in a row.
Note:
You can use the [*] consecutive repeat operator when you
specify a range of clocking events such as ##[1:9].
The following is a code example that uses expect statements:
module test;
logic log1,log2,clk;
initial
begin
log1=0;
log2=0;
clk=0;
#33 log1=1;
#27 log2=1;
#120 $finish;
end
always
#5 clk=~clk;
tbpb tbpb1(log1, log2, clk);
endmodule
program tbpb (input in1, input in2, input clk);
bit bit1;
initial
begin
e1: expect (@(posedge clk) ##1 in1 && in2)
begin
bit1=1;
$display("success at %0t in %m\n",$time);
end