User guide

24-204
SystemVerilog Testbench Constructs
called the success block. if false VCS executes the second
action blockafter the keyword else, called the failure block.
Here is another example of an expect statement. This one calls for
evaluating the expression after a range of clocking events.
e2: expect (@(posedge clk) ##[1:9] in1 && in2)
begin
. // statements VCS executes
. // if in1 && in2 is true
.
end
else
begin
. // Statements VCS executes
. // if in1 && in2 is false
.
end
This expression calls for evaluation the expression after 1, 2, 3, 4, 5,
6, 7, 8, and 9 clocking events, a range of clocking events from 1 to 9.
Here is another example of an expect statement. This one calls for
evaluating the expression to be true a number of times after the clock
delay.
e3: expect (@(posedge clk) ##1 in1 && in2 [*5])
begin
. // statements VCS executes
. // if in1 && in2 is true
.
end
else
begin
. // Statements VCS executes
. // if in1 && in2 is false
.
end