User guide

3-9
Compiling and Elaborating Your Design
• Assigning values to regs or memory elements at simulation time
0 when the value you assign is not the same as the value specified
with the +vcs+initreg or +vcs+initmem option.
For example:
initial
begin
mem[1][1]=8’b00000001;
.
.
.
Allowing Inout Port Connection Width Mismatches
By default it is an error condition if you connect a signal to an inout
port and that signal does not have the same bit width as the inout
port. It is a warning condition if you connect such a mismatched signal
to an input or output port.
You can use the +noerrorIOPCWM compile-time option to change
the error condition for an inout port to a warning condition, and thereby
allow VCS to create the simv executable. Consider the following
code:
module test;
wire [7:0] w1;
.
.
.
dev dev1 (w1);
.
.
.
endmodule
module dev(gk);
inout [15:0] gk;
.
.
.
endmodule