User guide

24-203
SystemVerilog Testbench Constructs
The following is an example of an expect statement:
e1: expect (@(posedge clk) ##1 in1 && in2)
begin
. // statements VCS executes
. // if in1 && in2 is true
.
end
else
begin
. // Statements VCS executes
. // if in1 && in2 is false
.
end
Where:
e1:
Is an instance name for the expect statement. You can use any
unique name you want, followed by a colon (:).
expect
The expect keyword.
(@(posedge clk) ##1 in1 && in2)
Is the property of the expect statement. Such properties are
enclosed in parentheses. This property is the following:
@(posedge clk)
the clock signal is clk, the clocking event is a rising edge
(posedge) on clk. Using the posedge keyword means that it,
with the clock signal, are an expression and so are also
enclosed in parentheses.
##1
Is a clock delay. It specifies waiting for one clocking event, then
evaluating the expression.
in1 && in2
Is an expression. If true, VCS executes the first action block