User guide

24-202
SystemVerilog Testbench Constructs
SystemVerilog Assertions Expect Statements
SystemVerilog assertions expect statements differ from assert,
assume, and cover statements in the following ways:
• expect statements must appear in a SystemVerilog programs,
whereas assert, assume, and cover statements can appear in
modules, interfaces, and programs.
• You can declare sequences and properties and use them as
building blocks for assert, assume, and cover statements, but
this is not true for expect statements. expect statements don’t
have sequences, neither explicitly or implicitly. expect
statements have properties, but properties are not explicitly
declared with the property keyword.
Note:
- assert, assume, and cover statements cannot appear in
clocking blocks.
- assert, assume, and cover statements can appear in
programs on an early availability basis.
In an expect statement you specify a clock signal and have the
option of specifying an edge for clocking events and delays, just like
assert and cover statements, but these are not followed by a
sequence, instead there is just a clock delay and an expression. There
are action blocks that execute based on the truth or falsity of the
expression. The clock delay can be a range of clocking events, and
VCS evaluates the expression throughout that range. You can specify
that the clock delay and evaluation of the expression must repeat a
number of times (you can’t both have a range of clocking events and
also use repetition).