User guide

24-201
SystemVerilog Testbench Constructs
sequence seq ;
@(ck1) a ##1 b ;
endsequence
A: assert property (@(ck1) a ##1 b) ;
N: assert property (seq) ;
In this example the clocking block named ck1 is specified a the clock
signal in the sequence and the two assertions. The clocking event in
the clocking block, posedge clk, becomes the clock signal.
Sequences and Properties in Clocking Blocks
You can enter sequences and properties in a clocking block and then
use them in an assertion. When you do, the clocking event for the
clocking block becomes the clock signal for the sequence or property.
The following is an example of a property in a clocking block:
clocking ck1 @(posedge clk) ;
property prop1;
a ##1 b ;
endproperty
endclocking
A: assert property (ck1.prop1) ;
Here property prop1 is declared in the clocking block named ck1. The
clock signal for the property is posedge clk. You enter the property
in an assertion by specifying the clocking block and then the property.