User guide

24-199
SystemVerilog Testbench Constructs
Synchronous Events
The event control operator, @, is used for explicit synchronization.
This operator causes a process to wait for a particular event (that is,
signal value change, or a clocking event) to occur.
Syntax
@ (expression);
expression
denotes clocking block input or inout, or a slice, which may include
dynamic indices. The dynamic indices are evaluated when
@(expression) executes.
For examples, see pages 189-190 of the SystemVerilog LRM3.1a
Synchronous Drives
The output (or inout) signals defined in a clocking block are used to
drive values onto their corresponding signals in the DUT at a specified
time. That is, the corresponding signal changes value at the indicated
clocking event as indicated by the output skew.
Note: For the syntax for specifying a synchronous drive, see section
15.14 of the SystemVerilog LRM 3.1a.
Consider the following clocking block and synchronous drives:
clocking cb1 @(posedge clk);
default output #2;
input #2 output #0 a = a1;
output b = b1;
endclocking