User guide

24-198
SystemVerilog Testbench Constructs
Any SystemVerilog expression that evaluates to a positive integer
value.
For example:
## 2;
## (x+1);
Note:
VCS issues a compilation error if you use a cycle delay without
specifying a default clocking block for the current module,
interface, or program.
Input Sampling
All inputs and inouts of a clocking block are sampled at the
clocking_event for that block. The following is skew related behavior
involving regions:
• When the skew is #0, the signal value in the Observed region
corresponds to the value sampled.
• When the skew is not #0, then the signal value at the Postponed
region of the timestep skew time-units prior to the clocking event
corresponds to the value sampled.
• When the skew is #1step, the signal value in the Preponed region
corresponds to the value sampled.
The last sampled value of signal replaces the signal when the signal
appears in an expression.
Note:
See section 14.3 of the SystemVerilog LRM 3.1a for definitions
of Observed, Postponed and Preponed regions.